1. Field of the Invention
The present invention relates to management of Test Access Port (TAP) functions and has been developed with particular attention paid to the possible application to systems on a single chip (systems on a chip—SOCs), in particular in compliance with the JTAG/IEEE 1149.1 Standard.
2. Description of the Related Art
The test standard JTAG/IEEE 1149.1 has been developed and has met with considerable success as regards the need to overcome the problems that are likely to arise, for example, in surface-mounted packages, in boards with components mounted on both faces (the so-called “double-sided boards), in multichip modules and, in general, in situations in which problems of gaining access to given signals may arise.
In particular, the standard in question makes it possible to carry out testing on circuits which otherwise could not be tested, a fact that implies the possibility of cutting down considerably on times and costs for developing and commercializing a product.
The standard in question enables a TAP configuration to be obtained based upon an architecture currently known as boundary scan.
This solution is based upon the possibility of providing, in the context of an integrated circuit, circuit elements that are able to perform functions of testing, maintenance and support of the circuit, even after the latter has been mounted, for instance, on a board.
The circuitry in question usually comprises a standard interface through which the test instructions and data are communicated. A set of testing characteristics are defined, including a so-called “boundary-scan register”, in such a way that the component may be able to respond to a minimum set of instructions defined so as to enable testing of the circuit.
In particular, the IEEE 1149.1 Standard defines the architecture of the TAP and of the corresponding circuits (which are essentially based upon a shift register) comprised in a device of the boundary-scan type. Each signal pin is connected to a cell of the shift register. The cells in question are connected in a path that may be likened to a shift register set along the periphery or boundary (hence, the term “boundary scan”) of the device, so as to supply a virtual access to the signal pins. Using the virtual access provided by the boundary-scan architecture, it is possible to provide a testing function, even in the framework of rather complex circuits, in conditions where physical access is not feasible.
The main advantage of the boundary-scan technique lies in the possibility of observing data on the inputs of the device, as well as control data on the device outputs, all of which are obtained regardless of the logic of the system implemented on the chip.
In addition, the boundary-scan technique provides a better diagnostic function than those offered by traditional testing techniques. Usually, a testing function of a traditional type envisages application of given signal configurations to the input pins and then observation of the response given by the circuit on the output pins. If there is a defect present on one of the input pins, traditional testing techniques are able to detect the existence of this defect, but in general they call for a rather complex investigation to identify which of the input pins is the defective one. Instead, the cells of a boundary-scan scheme observe the response of the circuit by monitoring the input pins, so that a test carried out using the boundary-scan technique makes it possible to determine very easily, for example, which input pin is not making contact with the circuit. Furthermore, this can be achieved even without the need to make a physical contact with the pin in question.
At least in principle, by making a set based totally on components operating according to a boundary-scan scheme, the shift-register paths of all the devices may be connected together to form a single path. In this way, it is possible to check and monitor the behaviour of all the pins and of all the interconnections of the device simply from an edge connector.
Traditionally, in the case of a SOC system, the TAP function is used for two main purposes.
In the first place, it is used to handle all the signals and the control and testing functions according to the JTAG/IEEE 1149.1 Standard.
In the second place, it is used as external connection for the debugging system present on the chip.
In the case of SOC systems in which a number of chips are integrated, there may arise the problem deriving from the fact that the corresponding TAP functions, one for testing and the other for debugging, must be made to operate on the same chip, using the same JTAG interface and hence preventing proliferation of the corresponding pins.